1. Field of the Invention
The present invention relates to a preamble length adjustment method in a communication network and an independent synchronization (independent point-to-point clocking) type serial data communication device which adopts such a preamble length adjustment method. More particularly, the present invention relates to implementation of a method and device which can maintain a preamble added to each frame of serial data within a range of suitable lengths at all times in any case.
2. Description of the Related Art
In a communication network which employs an independent synchronization type transmission system, each station connected to the network uses its autonomous clock for data transmission. Clock tolerances at stations are compensated for by adjusting a length of a preamble attached to data.
Almost every transmitter and receiver circuits connected to a communication network requires a duration of several bits from the time an input appears until a valid output is provided. For this reason, a bit string called a preamble is commonly added to a part preceding each data which constitutes a frame, whereby clock tolerance compensation is performed which permits the transmitter and receiver circuits to reach their steady states, i.e., the states in which they can send their valid outputs to a system. The length of the preamble in FDDI-II is typically 5 symbols (1 symbol=5 bits).
In such a communication network, since each station connected to the communication network uses its autonomous clock for data transmission, a cumulative phase difference of transmitted serial data, which results from subtle differences between the frequencies of the respective stations, may not be of negligible magnitude.
The process of formation of the cumulative phase difference is shown in FIGS. 15 and 16.
Referring to FIG. 15, a first station 1 to an n.sup.th station n are connected to the above-described communication network. It is assumed here that the first station 1, which receives serial data S0 transmitted at a transmission frequency f0, temporarily stores the serial data S0 in its buffer memory and transmits the stored data to a succeeding station, carries out the operation of reading out (transmitting) the stored data at an internal frequency f1 slightly lower than the transmission frequency f0. It is similarly assumed that a second station 2, which receives serial data S1 transmitted from the first station 1 (at the transmission frequency f1), temporarily stores the serial data S1 in its buffer memory and transmits the stored data to a succeeding station, carries out the operation of reading out (transmitting) the stored data at an internal frequency f2 slightly higher than the aforesaid frequency f1. It is similarly assumed that a third station 3, which receives serial data S2 transmitted from the second station 2 (at the transmission frequency f2), temporarily stores the serial data S2 in its buffer memory and transmits the stored data to a succeeding station, carries out the operation of reading out (transmitting) the stored data at an internal frequency f3 slightly higher than the aforesaid frequency f2. According to the above-described assumptions, the phases of the serial data S0 to S3 will exhibit variations as shown in FIGS. 16, (a) to (d), respectively. If the shown phase differences are accumulated, an overflow or an underflow will occur in the aforesaid buffer memory for the aforesaid temporary data storage in a certain succeeding station. As a result, there may be a case where even the normal operation of such a station cannot be ensured.
To cope with the above-described problems, each station has conventionally been provided with a device of the type shown in FIG. 17 so that the above-described phase differences can be absorbed by increasing or decreasing the length of the preamble (a part PA of each serial data, indicated by oblique hatching in FIG. 16).
In the device shown in FIG. 17, an internal clock source 11 serves as a part for generating a clock signal which determines the operating frequency of an associated station, and an elasticity buffer 12 and a smoothing buffer 13 each serves as a part for temporarily storing the aforesaid serial data by a FIFO (first-in/first-out) method. A clock derivator 14 derives a transmitted clock from input serial data and writes the input serial data to the elasticity buffer 12 on the basis of the derived clock WC1. A buffer capacity detector 15 detects the amount of data written to the elasticity buffer 12, that is, the amount of memory of the elasticity buffer 12 which is used each time writing is performed. A clock phase controller 16 provides control to shift (advance or delay) the phase of a clock generated by the internal clock source 11 on the basis of the detection output of the buffer capacity detector 15 and reads out the data stored in the elasticity buffer 12 on the basis of a clock RC1 having the thus-obtained controlled phase in order to absorb through the elasticity buffer 12 the phase deviation of data due to the above-described frequency differences between the stations. A preamble length detector 17 detects the length of the preamble PA contained in the serial data read from the elasticity buffer 12 (for example, detects the preamble PA and counts the length thereof). A buffer capacity detector 18 detects the amount of memory of the smoothing buffer 13 which is used for each writing operation. A clock phase controller 19 provides control to shift the phase of a clock generated by the internal clock source 11 on the basis of the detection output of each of the preamble length detector 17 and the buffer capacity detector 18 and writes the serial data read from the elasticity buffer 12 to the smoothing buffer 13 on the basis of a clock WC2 having the thus-obtained controlled phase in order to increase or decrease the length of the preamble PA through the smoothing buffer 13. The data thus written to the smoothing buffer 13 is read out on the basis of a clock RC2 generated by the internal clock source 11, and is outputted from the corresponding station as data to be transmitted to the succeeding station.
The following description refers to several typical examples of a conventional method of controlling the smoothing buffer 13 by means of the device shown in FIG. 17, particularly the clock phase controller 19, that is to say, a conventional adjustment method for a preamble length, and the control algorithms of each of the conventional examples is also set forth.
1) First Method (hereinafter referred to as a "limit smoother" for convenience's sake)
In this method, if the length of a preamble is 4 to 6 symbols, the preamble is transmitted as received, and if the length of the preamble is either 3 symbols or less or 7 symbols or more, adjustment of the length of the preamble is performed. Control algorithms are as follows.
(a) The smoothing buffer 13 is placed in 50% utilization condition at the time of resetting of a network.
(b) The smoothing buffer 13 is made to perform its FIFO operation with respect to each part of data other than a preamble part. More specifically, symbols are taken out of the smoothing buffer 13 and are transmitted until a succeeding preamble appears.
(c) In a case where the detected preamble has a length of 3 symbols or less and a starting delimiter of the succeeding cycle (the identification code attached to the leading part of the cycle) appears in an output of the buffer 13, if the utilization of the buffer 13 is less than 100%, the preamble is transmitted instead of the starting delimiter and the input from the preceding station is buffered. If the utilization of the buffer 13 reaches 100% or if the length of the transmitted preamble increases to 4 symbols, transmission of the succeeding cycle is started with the starting delimiter positioned in the leading part of the buffer 13.
(d) The number of symbols of the preamble which is being transmitted is counted. If 6 symbols are transmitted and no starting delimiter of the succeeding cycle appears in the output of the buffer 13, preambles are taken and discarded from the buffer 13 until the starting delimiter appears. If the starting delimiter has not yet been buffered, the buffer 13 becomes empty in this step. Therefore, the process awaits the arrival of the starting delimiter while retransmitting the preambles.
2) Second Method (hereinafter referred to as a "centering smoother" for convenience's sake)
In a case where the aforesaid limit smoother transmits the preamble of 4 or 6 symbols, if the utilization of the buffer 13 can be made to approach 50% by making the length of the preamble 5 symbols, the preamble of 5 symbols is transmitted instead of the preamble of 4 or 6 symbols in the following way.
(a) The smoothing buffer 13 is placed in 50% utilization condition at the time of resetting of a network.
(b) The smoothing buffer 13 is made to perform its FIFO operation with respect to each part of data other than a preamble part. More specifically, symbols are taken out of the smoothing buffer 13 and are transmitted until a succeeding preamble appears.
(c) In a case where the length of a preamble to be transmitted is 3 symbols or less and the starting delimiter of the succeeding cycle appears in the output of the buffer 13 and where the utilization of the buffer 13 is less than 100%, the preamble is transmitted instead of the starting delimiter and the input from the preceding station is buffered.
c-1) When the utilization of the buffer 13 reaches 100%; or
c-2) when the utilization of the buffer 13 exceeds 50% and the length of the transmitted preamble increases to 4 symbols; or
c-3) when the utilization of the buffer 13 is 50% or less and the length of the transmitted preamble increases to 5 symbols,
transmission of the succeeding cycle is started with the starting delimiter positioned in the leading part of the buffer 13.
(d) The number of symbols of the preamble which is being transmitted is counted.
d-1) A preamble of 5 symbols is transmitted, and if and as long as the utilization of the buffer 13 exceeds 50%, preambles remaining in the buffer 13 are read out and discarded until the starting delimiter appears in the output of the buffer 13. If the utilization of the buffer 13 decreases to 50% (or less) during discarding of the preambles, the process proceeds to the next d-2).
d-2) The preambles are taken out and transmitted from the buffer 13. If the length of the preamble amounts to 6 symbols, as long as the buffer 13 is not empty, the preambles are read out and discarded from the buffer 13 until the starting delimiter appears. If no starting delimiter has yet been buffered, the buffer 13 becomes empty in this step. Therefore, the process awaits the arrival of the starting delimiter while transmitting the preambles.
3) Third Method (hereinafter referred to as a "target smoother" for convenience's sake)
In this method, the length of a preamble is made to approach 5 symbols as long as the capacity of the buffer 13 permits. Control algorithms are as follows.
(a) The smoothing buffer 13 is placed in 50% utilization condition at the time of resetting of a network.
(b) The smoothing buffer 13 is made to perform its FIFO operation with respect to each part of data other than a preamble part. More specifically, symbols are taken out of the smoothing buffer 13 and are transmitted until a succeeding preamble appears.
(c) In a case where the length of a preamble to be transmitted is 4 symbols or less and a starting delimiter of a succeeding cycle appears at the output of the buffer 13 and where the utilization of the buffer 13 is less than 100%, the preamble is transmitted instead of the starting delimiter and the input from the preceding station is buffered. If the utilization of the buffer 13 reaches 100%, transmission of the succeeding cycle is started with the starting delimiter positioned in the leading part of the buffer 13.
(d) The number of symbols of a preamble which is being transmitted is counted. After a preamble of 5 symbols has been transmitted, as long as the buffer 13 is not empty, preambles are read and discarded from the buffer 13 until the starting delimiter appears. If the starting delimiter has not yet been buffered, the buffer 13 becomes empty in this step. Therefore, the process awaits the arrival of the starting delimiter while transmitting the preambles.
The above-described examples are conventional representative preamble length adjustment methods. As for documents relating to the above-described preamble length adjustment methods, the following reports are known which are contained in ANSI (American National Standards Institute) working paper:
(A) DRAFT PROPOSED ANS "FDDI HYBRID RING CONTROL" (Aug. 12, 1988) P.32 to P.38;
(B) David Dodds "JITTER CONTROL IN FDDI-II SYSTEMS" (Sep. 30, 1987); and
(C) David Dodds "JITTER CONTROL IN FDDI-II SYSTEMS Progress Report" (Jul. 8, 1987).
As is apparent from FIG. 17, in any of the above-described conventional preamble length adjustment methods, the phase deviation of data due to the frequency differences between stations is absorbed through an elasticity buffer, and a preamble length, which has been adjusted to be extremely short or long by the absorption of the phase deviation, is corrected through a smoothing buffer. Accordingly, in such a method, if successive cycles (frames) of short preambles arrive at a certain station, the smoothing buffer operates to successively restore the preamble lengths and may use up its allowable buffer capacity in several cycles. In such a case, it follows that the subsequent cycles of serial data are sent to a succeeding station without any correction. As a result, if transmitted serial data are passed through a multiplicity of stations and the aforesaid adjustment is repeated for the same cycle, the preamble length of such a cycle is progressively reduced and a length of 0 symbols (the absence of a preamble) might result. This result means that the subsequent adjustment is applied to a data portion and data destruction might be caused.